The present invention relates generally to semiconductor memory devices, e.g., DRAMs, and more particularly, to a column redundancy circuit therefor.
One of the major determinants of the cost of producing memory chips is wafer yield, which is defined as the ratio of non-defective chips/total chips fabricated on a given wafer. In general, the higher the integration density of the memory chip, the higher the probability that one or more memory cells thereof will be defective. Thus, the higher the integration density of the chips fabricated on a given wafer, the lower the wafer yield. Accordingly, the need for a method in which to correct defects in order to enhance wafer yield became more acute with the advent of high-density memory chips.
The single most effective method in which to correct memory cell defects in order to enhance wafer yield is the provision of a redundant memory circuit in which one or more redundant rows and/or columns of memory cells are provided in order to replace rows and/or columns of the main memory array which are found to be defective, during testing, e.g., during wafer sort. In general, the redundant rows and/or columns have initially unspecified addresses and redundant decoders coupled thereto. The redundant decoders are programmable in such a manner as to match the addresses of rows and/or columns which are determined to be defective. The defective rows and/or columns are decoupled or disabled.
In operation, when a memory read or write cycle is executed, access to the defective rows and/or columns is prevented, and the redundant decoders are responsive to only the addresses of the defective rows and/or columns, to thereby effectively replace the defective rows and/or columns with the redundant rows and/or columns, which are sometimes referred to as spare rows and/or columns. This technique of replacing defective rows and/or columns with redundant rows and/or columns is oftentimes referred to as repairing defective memory cells.
A typical implementation of the programmable redundant decoder is an address decoder in which a polysilicon fusible link, i.e., fuse, is connected to each address bit line of a row address or column address buffer, depending upon whether the redundant decoder is a redundant row or column decoder, respectively. In order to program such a redundant decoder with the address of a column or row of memory cells having a defective memory cell, selected ones of the fuses are cut/blown, e.g., by means of a laser.
With reference now to FIG. 1, there can be seen a representational block diagram of the organizational structure of a multi-block memory device and the row and column address decoders therefor. As can be seen, the memory device depicted in FIG. 1 includes an m.times.n normal memory cell array and an m.times.k redundant memory cell array. In operation, fuse boxes FB1-FBk generate signals .phi.REN1-.phi.RENk, respectively, which indicate the receipt of a column address signal corresponding to a defective column in the normal memory cell array. More particularly, if a column common to normal cell arrays NCA12-NCAm2 is determined to contain a defective memory cell, then the signal .phi.REN2 will be driven high. The normal decoder control circuit NDC, in response to the signal .phi.REN2 being driven high, will disable the input/output gates IO12-IOm2 corresponding to the normal cell arrays NCA12-NCAm2, respectively, which share the defective column, by way of disabling the normal column decoder NCD2 corresponding to the defective column. Further, the signals .phi.REN1-.phi.RENk generated by the fuse boxes FB1-FBk, respectively, are also applied to redundant column decoders RCD1-RCDk, respectively. The redundant column shared by the redundant cell arrays RCA12-RCAm2 is selected by the corresponding redundant column decoder RCD2, in response to the signal .phi.REN2 going high, thus effectively replacing the defective column with the redundant column which has been programmed with the address of the defective column.
With reference now to FIG. 2, there can be seen an overall block diagram of the conventional column redundancy circuit, including a redundant column control circuit 100', a fuse box array 200', and a redundant column driver 300'. More particularly, the redundant column control circuit 100', in response to receipt of a row address signal corresponding to that of a defective memory cell, generates a redundancy enable signal RSTP which is applied to a first input of the fuse box array 200'. The fuse box array 200' also receives, at a second input, a column address signal. When the fuse box 200' receives a high logic level RSTP signal at its first input, and a column address signal corresponding to a defective column at its second input, it generates a high logic level output signal, .phi.RENi, which is referred to as the redundancy sensing signal. The redundancy sensing signal .phi.RENi is applied to the redundant column driver 300' which, in response to the signal .phi.RENi, generates an output signal RCSL which activates the redundant or spare column RCAi which has been selected to replace the defective column.
With reference now to FIG. 3, there can be seen a detailed circuit diagram of the fuse box 200' of the conventional column redundancy circuit depicted in FIG. 2. In operation, the fuse box array 200' works as follows. More particularly, in response to the RSTP signal going high, the output signal "b" of the inverter 7 goes high, and the output signal "a" of the inverter 6 goes low, thereby turning on the dual transistors T1 and T2 in the fuse box 200'A of the fuse box array 200'. Assuming that the fuse F1 of the fuse box 200'A has been blown, then the node r1 will remain high, even when the column address bit CAi associated therewith is low. Thus, assuming that negative logic is used, the fuse box 200'A has been programmed to generate a high level signal as its output node r1 only in response to receipt of the column address bit CAi. If the remaining fuse boxes CA2-9 also have their fuses selectively blown in a similar manner, then the fuse box array 200' can be programmed with the column address of the defective column. Thus, the fuse box array 200' can be considered a programmable redundant column address decoder. When the column address corresponding to the defective column is received, it generates an output signal .phi.RENi having a high logic level. As described previously in conjunction with FIGS. 1 and 2, this signal is then applied to the redundant column driver 300' to activate the selected redundant column for replacing the defective column.
A significant drawback with the above-described conventional column redundancy circuit is that the entire defective column common to several memory sub-arrays is disabled, even though only a portion thereof located within a single one of the sub-arrays may in fact be defective, i.e., the only defective memory cell(s) connected to the defective column may be contained within a single one of the sub-arrays. This results in unnecessary loss of memory space. Moreover, this results in unnecessary usage of valuable and scarce redundant memory space, thereby reducing redundancy efficiency and the, wafer yield.
In order to overcome this limitation, the present inventor has proposed the column redundancy circuit disclosed in U.S. patent application Ser. No. 757,465, entitled "Semiconductor Memory Redundant Device". A partial schematic, partial block diagram of a fuse box utilized in this proposed column redundancy circuit is depicted in FIG. 4. As is evident from FIG. 4, in this proposed column redundancy circuit, the redundancy efficiency is improved by virtue of employing a block selection signal .phi.BLSki which is applied to a block decoder corresponding to each specific sub-array/memory block of the memory device, to thereby facilitate repair of only the column of the specific memory block which contains the defective memory cell, rather than all of the memory blocks or sub-arrays which share the defective column. Although this proposed column redundancy circuit constitutes a major improvement over theretofore existing technology, it suffers from the following shortcoming. More particularly, when it is necessary to replace the same column in two or more different memory blocks, the circuit is incapable of doing this, thereby limiting the utility thereof.
Based upon the foregoing, it can be appreciated that there presently exists a need for a column redundancy circuit for a semiconductor memory device which overcomes the above-described limitations and disadvantages of the presently available column redundancy circuits. The present invention fulfills this need.